A ferroelectric random access memory (FeRAM) generally includes an array of FeRAM cells where each FeRAM cell contains at least one ferroelectric capacitor. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store a data bit in an FeRAM cell, a write operation applies write voltages to the plates of the ferroelectric capacitor in the FeRAM cell to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed and thus provides non-volatile storage of the stored data bit.
A conventional read operation for an FeRAM determines the data bit stored in an FeRAM cell by connecting one plate of a ferroelectric capacitor to a bit line and raising the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small charge and voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large charge and voltage increase on the bit line. A sense amplifier can determine the stored value from the resulting bit line current or voltage.
Development, manufacture, and use of an integrated circuit such as FeRAM generally requires testing that determines the characteristics of the integrated circuit and determines whether the integrated circuit is functioning properly. One important test for an FeRAM is measurement of the charge delivered to bit lines when reading memory cells. Generally, the bit line charge or voltage that results from reading an FeRAM cell varies not only according to the value stored in the FeRAM cell but also according to the performance of the particular FeRAM cell being read. Developers of an integrated circuit containing FeRAM arrays often want to measure the distribution of delivered charge because such information is critical to selecting operating parameters that eliminate or minimize errors when reading or writing data. When manufacturing integrating circuits containing FeRAM arrays, measuring the charge distribution can indicate whether a particular integrated circuit is defective or whether a repair operation is required. IC manufacturers could also use the charge distribution measurements to adjust or select operating parameters for optimal performance in a specific IC. Similarly, during use of an FeRAM, an on-chip test that measures the distribution of bit line charge for read operation would be useful to an automated diagnostic of the FeRAM or automatic adjustment of the operating parameters of the FeRAM.
An article by Jeon et al., entitled xe2x80x9cA 0.4-xcexcm 3.3-V 1T1C 4-Mb Nonvolatile Ferroelectric RAM with Fixed Reference Voltage Scheme and Data Protection Circuitxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, November 2000, describes results from measuring the charge distribution for 4-Megabit FeRAM. For each FeRAM cell, the described measurement included writing a binary value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d to the FeRAM cell, charging a reference line to one of a series of charge levels, reading out a charge from the FeRAM cell to a bit line, and sensing whether the bit line or the reference bit line has a higher voltage. The process must repeat charging the reference line and reading out the charge from the FeRAM cell for each of the charge levels used in measuring the distribution. Further, the entire series is repeated for each data value xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. This charge distribution measurement for a 4-Megabit FeRAM can take several minutes. The time required for the distribution measurement may be acceptable during development of an integrated circuit when a relatively small number of devices are tested, but in production, the lengthy test time can reduce manufacturing throughput and increase costs. For on-chip testing, the lengthy test time is generally unacceptable.
Another problem with current bit line charge distribution measurements for FeRAM is repeated readout of charge from each of the FeRAM cells. The readout operation generally writes-back or refreshes the data value stored in the memory cell. This can lead to inconsistency in the distribution measurement when the charge from an FeRAM cell varies for each readout operation. The repeated readout operations that refresh the data value can also lead to imprinting, which results when repeated writing of the same value changes the response of the memory cell. Further, repeated readout, which refreshes the stored value, can mask retention problems or time-dependent changes in delivered charge since the charge read out almost always corresponds to a freshly written or refreshed data value.
In view of the current limitation of methods for measuring charge distributions of FeRAMs, structures and methods that allow faster determinations of the charge distributions are sought.
In accordance with an aspect of the invention, an on-chip circuit measures the distribution of bit line voltages or charge resulting from reading FeRAM cells. The measurement employs a comparator-type sense amplifier that without disturbing the bit line voltage compares the bit line voltage to a series of reference voltages (e.g., 100 different levels). For each comparison during testing, the sense amplifier generates a binary result value indicating whether or not the bit line voltage is greater than the current reference voltage. The bit line voltage is kept constant throughout the series of comparisons, which avoids delays, measurement inconsistencies, and endurance problems that arise in conventional processes that repeatedly read an FeRAM cell for a series of comparisons. Measurement times, which are shortened by avoiding repeated readout operations, can be further reduced by simultaneously operating multiple sense amplifiers in the FeRAM to simultaneously test multiple FeRAM cells in an array. The binary result values associated with the comparisons can be output for external analysis or used internally to identify defects or to update or select operating parameters.
The measurement techniques not only provide fast distribution measurements but can also test data retention. One data retention test process writes data values in the FeRAM cells and then bakes the FeRAM or otherwise ages the stored data before performing the charge distribution measurement. Since charge is read out of an FeRAM cell once and measured without refreshing the stored data, the charge distribution measurement accurately reflects the aging of stored data. The aged distribution can be compared to a distribution measured immediately after writing data values in the FeRAM.
The same on-chip circuits and techniques for measuring charge distribution can measure the performance of the sense amplifiers. If the bit line is grounded or biased to a known voltage while stepping the reference voltage through the series of voltage levels, each sense amplifier provides a binary output signal that changes when the reference voltage reaches the level causing the sense amplifier to trip. The distribution of voltages thus measured characterizes the performance of the sense amplifiers and indicates whether any sense amplifiers are defective.
One specific embodiment of the invention is a method for testing an integrated circuit containing FeRAM cells. For each FeRAM cell being tested, the method generally includes: (a) reading out a charge from the FeRAM cell to a bit line; (b) biasing a reference line to a first/next voltage from a series of reference voltages; (c) generating a result signal indicating whether the voltage on the reference line is higher than a voltage on the bit line; and (d) keeping the charge/voltage on the bit line constant while repeating steps (b) and (c) until the reference line has been biased to a last reference voltage of the series. A comparator-type sense amplifier connected to the bit and reference lines can generate the result signal without disturbing the bit line voltage. The test thus quickly generates a series of result signals for each FeRAM cell without repeated readout from each FeRAM cell. Optionally, stored values in the FeRAM can be aged before reading charge from the FeRAM cells.
Each result signal for an FeRAM cell is generally a binary signal and corresponds to one of the reference voltages. The series of reference voltages is generally a monotonic increasing or decreasing series of voltages so that the series of binary result signals for an FeRAM cell changes value (e.g., 0 to 1 or 1 to 0) when the reference voltage approximately matches the bit line voltage arising from reading charge out of the FeRAM cell. The result signals generated thus can be used to determine the bit line voltages read from the FeRAM cells and a charge distribution for readout from the FeRAM cells.
In accordance with another aspect of the invention, on-chip circuits in the integrated circuit perform the tests. The result signals generated by on-chip testing can be output for analysis or used on-chip for defect detection or for on-chip self-tuning that sets operating parameters such as a reference voltage used during read operations.
Another embodiment of the invention is an integrated circuit including: an array of FeRAM cells; a reference voltage generator; sense amplifiers connected to bit lines of the array and to the reference voltage generator; and an on-chip control circuit coupled to the reference voltage generator and the sense amplifier. The on-chip control circuit operates the reference voltage generator and the sense amplifiers to sense bit line voltages and generate data indicating a distribution for charge read out of the FeRAM cells. For fast operation, each sense amplifier leaves the bit line voltage undisturbed when generating a result signal indicating whether the bit line voltage is greater than a reference voltage from the reference voltage generator. In a test mode, the on-chip control circuit causes the reference voltage generator to sequentially supply to the sense amplifiers a series of reference voltages, while bit line voltages remain constant. For each of the reference voltages, each sense amplifier generates a result signal indicating whether a corresponding bit line voltage is greater than that reference voltage.
An on-chip output circuit can directly output the result signals from the sense amplifiers. Instead of or in addition to outputting the result signals, an on-chip adjustment circuit can use the results signals in selecting an operating parameter such as a reference voltage for read operations.